1. Technical Field
This description generally relates to the field of chip packaging, and more particularly to fan-out wafer level packaging.
2. Description of the Related Art
Redistributing the bond pads of integrated circuits (“ICs”) in chip packages is becoming increasingly common. In general, the redistribution process converts peripheral wire bond pads on an IC to an area array of solder bumps via a redistribution layer. The resulting fan-out wafer level packaging may have a larger solder bump bonding area and may be more easily integrated into electronic devices and larger chip packages.
Referring to FIG. 1, conventional fan-out wafer level packaging is illustrated. Conventionally, a backside of an IC 2 is first encapsulated in a molding compound 1. A plurality of dielectric layers 4 and redistribution layers 3 are then deposited on a front side of the IC 2 to form electrical connections between wire bond pads 7 on the IC 2 and redistributed solder bump bond pads 5. Finally, solder bumps 6 are formed at the redistributed bond pad locations 5, and the fan-out wafer level packaging is ready to be soldered to a printed circuit board.
FIG. 2 illustrates the encapsulation process as applied to a plurality of ICs 2 arranged on a surface, such as a tape 8 on a carrier 9. The mold compound 1 is dispensed centrally on the tape 8 at a thickness sufficient to completely cover all exposed surfaces of each IC 2. The ICs 2 are placed in a mold chase 10 that is configured to compress the molding compound 1 down and around all of the ICs 2. A large amount of molding compound 1 is required to ensure that all side surfaces and the backside of each IC 2 is completely covered.
As shown in FIG. 3, prior to compressing the mold compound 1 down around the ICs 2 a protective film 11 is arranged over the molding compound 1 and across exterior edges 12, 13 of the mold chase. The protective film 11 decreases the amount of compressive force applied to the ICs 2. Subsequently, the molding compound 1 is compressed down and spreads around each of the ICs 2.
Unfortunately, after employing such packaging methods, the backside of the IC 2 is typically covered by a relatively thick layer of the molding compound 1, as illustrated in FIG. 1. As a result, this can result in increased warping of the packaging due to coefficient of thermal expansion mismatch, and the thickness of the packaging.
There remains a need in the art, therefore, for an improved method of manufacturing fan-out wafer level packaging.